This invention generally relates to electronic design automation apparatus and, more particularly, to an improved critical path analyzer, also referred to as a timing analyzer or timing verifier.
Logic simulation is now an important tool in the design and verification of electronic circuits, including transistor level, gate level, and block level designs. Simulation tests the function of a design by exercising and evaluating circuit logic with a set of input patterns called test vectors. Logic simulators available today have simplified the generation of test vectors and made simulation a time- and cost-efficient method of uncovering many circuit-behavior problems before test-program development or production. A thorough simulation can reveal a variety of errors such as reversed polarities, missed clock periods, or incorrect logic implementation.
Simulation, however, cannot provide complete information about timing errors that occur in circuits employing sequential logic. Signal propagation in sequential logic circuits is not simultaneous. Propagation delays, for example, may influence the arrival time of signals at the several inputs of a single gate. If a signal misses a clock period as the result of such delay, simulation might show an error, but it may not report the signal path that introduced the critical delay. Moreover, if the delay occurs under conditions not exercised by the test vectors, simulation might miss the timing error entirely.
Timing analyzers provide the timing analysis lacking in logic simulators and allow a designer to identify signal paths whose timing is of concern. A signal path is considered to be a sequence of pins through a design that a signal will follow. Although path analysis approaches vary, at the heart of any path-analysis method is the concept of the critical path--the slowest of all signal propagation paths during a given cycle of circuit operation. A timer analyzer that provides critical path analysis typically searches for and identifies the fastest and slowest paths to a destination register in the circuit such as a clocked circuit element.
Prior timing analyzers, nevertheless, suffer from a number of drawbacks that limit their ease of use. One drawback is the difficulty in collecting information on different critical paths in the design. Information on each path is typically found in separate locations throughout the output from the analyzer, either on separate sheets of a printout or on separate terminal screen displays. A designer wanting to gather the different path information together must spend considerable time searching the output for the desired information and then record it.
Another drawback is the difficulty in visually tracing the critical path across the schematic sheets of the circuit. Most timing analyzers merely provide a textual description of the critical path, identifying the path by source and destination pins. It is left to the designer to trace the critical path across one or more schematic sheets to determine the path's circuit components and related signal delays. This process is not only time-consuming, but prone to error. Recognizing this, a timing analyzer available from Silicon Design Automation of San Jose, Calif., is constructed to highlight all critical paths directly on the schematic sheet when viewed on a terminal screen and to indicate delays for each component along path. But this analyzer still requires the designer to page through several screen displays of schematic sheets to view the entire signal path if the path crosses more than one schematic sheet.